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w29c020c 256k 8 cmos flash memory publication release date: april 2000 - 1 - revision a2 general description the w29c020c is a 2 - megabit, 5 - volt only cmos flash memory organized as 256k 8 bits. the device can be written (erased and programmed) in - system with a standard 5v power supply. a 12 - volt v pp is not required. the unique cell architect ure of the w29c020c results in fast write (erase/program) operations with extremely low current consumption compared to other comparable 5 - volt flash memory products. the device can also be written (erased and programmed) by using standard eprom programmers. features single 5 - volt write (erase and program) operations fast page - write operations - 128 bytes per page - page write (erase/program) cycle: 10 ms (max.) - effective byte - write (erase/program) cycle time: 39 m s - optional software - protected data write fast chip - erase operation: 50 ms two 8 kb boot blocks with lockout whole chip cycling: 10k (typ.) read access time: 70/90/120 ns twenty - year data retention software and hardware data protection low power consumption - active current: 25 ma (typ.) - standby current: 20 m a (typ.) automatic write (erase/program) timing with internal v pp generation end of write (erase/program) detection - toggle bit - da ta polling latched address and data all inputs and outputs directly ttl compatible jedec standard byte - wide pinouts available packages: 32 - pin 600 mil dip, 32 - pin tsop, and 32 - pin plcc
w29c020c - 2 - pin configurations block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq0 dq1 dq2 gnd a7 a6 a5 a4 a3 a2 a1 a0 nc a16 a15 a12 v we a14 a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 dd a17 32-pin dip 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 d q 2 g n d d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 oe a10 ce dq7 a 1 2 a 1 6 n c v d d / w e a 1 5 a 1 7 32-pin plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a3 a2 a1 a0 dq0 dq1 dq2 gnd oe a10 ce dq7 dq6 dq5 dq4 dq3 32-pin tsop a15 a12 a7 a6 a5 a4 v we a14 a13 a8 dd a11 a9 nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 a17 decoder core array control output buffer ce oe we a0 a17 . . . dq0 dq7 . . 8k byte boot block (optional) 8k byte boot block (optional) v v dd ss pin description symbol pin name a0 - a17 address inputs dq0 - dq7 data inputs/outputs ce chip enable oe output enable we write enable v dd power supply gnd ground nc no connection
w29c020c publication release date: april 2000 - 3 - revision a2 functional descripti on read mode the read operation of the w29c020c is controlled by ce and oe , both of which have to be low for the host to obtain data from the outputs. ce is used for device selection. when ce is high, the chip is de - selected and only standby power will be consumed. oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce or oe is high. refer to the read cycle timing waveforms for further details. page write mode the w29c020c is written (erased/programmed) on a page basis. every page contains 128 bytes of data. if a byte of data within a page is to be changed, data for the entire page must be loaded into the device. any byte that is not loaded will be erased to "ff hex" during the write operation of the page. the write operation is initiated by forcing ce and we low and oe high. the write procedure consists of two steps. step 1 is the byte - load cycle, in which the host writes to the page buffer of the device. step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written into the memory array for non - volatile storage. during the byte - load cycle, the addresses are latched by the falling edge of either ce or we , whichever occurs last. the data are latched by the rising edge of either ce or we , whichever occurs first. if the host loads a second byte into the page buffer within a byte - load cycle time (t blc ) of 200 m s after the initial byte - load cycle, the w29c020c will stay in the page load cycle. additional bytes can then be loaded consecutively. the page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded into the page buffer a7 to a17 specify the page add ress. all bytes that are loaded into the page buffer must have the same page address. a0 to a6 specify the byte address within the page. the bytes may be loaded in any order; sequential loading is not required. in the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. before the completion of the internal write cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. software - protected data write the device provides a jedec - approved optional software - protected data write. once this scheme is enabled, any write operation requires a three - byte command sequence (with specific data to a specific address) to be performed before the data load operation. the three - byte load command sequence begins the page load cycle, without which the write operation will not be activated. this write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power - up and power - down. the w29c020c is shipped with the software data protection enabled. to enable the software data protection scheme, perform the three - byte command cycle at the beginning of a page load cycle. the device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three - byte command sequence cycle. once enabled, the software data protection will remain enabled unless the disable commands are issued . a power transition will not reset the software data protection feature. to reset the device to unprotected mode, a six - byte command
w29c020c - 4 - sequence is required. for information about specific codes, see the command codes for software data protection in the table of operating modes. for information about timing waveforms, see the timing diagrams below. hardware data protection the integrity of the data stored in the w29c020c is also hardware protected in the following ways: (1) noise/glitch protection: a we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the write operation is inhibited when v dd is less than 2.5v. (3) write inhibit mode: forcing oe low, ce high, or we high will inhibit the write operation. this prevents inadvertent writes during power - up or power - down periods. (4) v dd power - on delay: when v dd reaches its sense level, the device will automatically timeout for 5 ms before any write (erase/program) operation. chip erase modes the entire device can be erased by using a six - byte software command code. see the software chip erase timing diagram. boot block operation there are two boot blocks (8k bytes each) in this device, which can be used to store boot code. one of them is located in the first 8k bytes and the other is located in the last 8k bytes of the memory. the first 8k or last 8k of the memory can be set as a boot block by using a seven - byte command sequence. see comman d codes for boot block lockout enable for the specific code. once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. once the boot block programming lockout feature is activated, the chip erase function will be disabled. in order to detect whether the boot block feature is set on the two 8k blocks, users can perform a six - byte command sequence: enter the product identification mo de (see command codes for identification/boot block lockout detection for specific code), and then read from address "00002 hex" (for the first 8k bytes) or "3fff2 hex" (for the last 8k bytes). if the output data is "ff hex," the boot block programming lockout feature is activated; if the output data is "fe hex," the lockout feature is deactivated and the block can be programmed. to return to normal operation, perform a three - byte command sequence to exit the identification mode. for the specific code, see command codes for identification/boot block lockout detection. data polling (dq7) - write status detection the w29c020c includes a data polling feature to indicate the end of a write cycle. when the w29c020c is in the internal write cycle, any attempt to read dq7 from the last byte loaded during the page/byte - load cycle will receive the complement of the true data. once the write cycle is completed. dq7 will show the true data. see the oe polling timing diagram.
w29c020c publication release date: april 2000 - 5 - revision a2 toggle bit (dq6) - write st atus detection in addition to data polling, the w29c020c provides another method for determining the end of a write cycle. during the internal write cycle, any consecutive attempts to read dq6 will produce alternating 0's and 1's. when the write cycle is completed, this toggling between 0's and 1's will stop. the device is then ready for the next operation. see toggle bit timing diagram. product identification the product id operation outputs the manufacturer code and device code. the programming equipment automatically matches the device with its proper erase and programming algorithms. the manufacturer and device codes can be accessed through software or by hardware operation. in the software access mode, a six - byte command sequence can be used to access the product id. a read from address "00000 hex" outputs the manufacturer code "da hex." a read from address "00001 hex" outputs the device code "45 hex." the product id operation can be terminated by a three - byte command sequence. in the hardware access mod e, access to the product id is activated by forcing ce and oe low, we high, and raising a9 to 12 volts. table of operating m odes operating mode selection operating range: 0 to 70 c (ambient temperature), v dd = 5v 10%, v ss = 0v, v hh = 12v mode pins ce oe we address dq. read v il v il v ih a in dout write v il v ih v il a in din standby v ih x x x high z write inhibit x v il x x high z/d out x x v ih x h igh z/d out output disable x v ih x x high z 5 - volt software chip erase v il v ih v il a in d in product id v il v il v ih a0 = v il ; a1 - a17 = v il ; a9 = v hh manufacturer code da (hex) v il v il v ih a0 = v ih ; a1 - a17 = v il ; a9 = v hh device code 45 (hex)
w29c020c - 6 - command codes for software data protection byte sequence to enable protection to disable protectio n address data address data 0 write 5555h aah 5555h aah 1 write 2aaah 55h 2aaah 55h 2 write 5555h a0h 5555h 80h 3 write - - 5555h aah 4 write - - 2aa ah 55h 5 write - - 5555h 20h software data protection acquisition flow software data protection enable flow load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 software data protection disable flow sequentially load up to 128 bytes of page data pause 10 ms exit pause 10 ms exit (optional page-load operation) notes for software program code: data format: dq7 - dq0 (hex) address format: a14 - a0 (hex)
w29c020c publication release date: april 2000 - 7 - revision a2 command codes for software chip erase byte sequence address data 0 write 5555h aah 1 write 2aaah 55h 2 write 5555h 80h 3 write 5555h aah 4 write 2aaah 55h 5 write 5555h 10h software chip erase acquisition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 10 to address 5555 pause 50 ms exit notes for software chip erase: data format: dq7 - dq0 (hex) addre ss format: a14 - a0 (hex)
w29c020c - 8 - command codes for product identification and boot block lockout detection byte sequence alternate product (7 ) identification/boot block lockout detection en try software product identification/boot block lockout detection en try software product identification/boot block lockout detection ex it address data address data address data 0 write 5555 aa 5555h aah 5555h aah 1 write 2aaa 55 2aaah 55h 2aaah 55h 2 write 5555 90 5555h 80h 5555h f0h 3 write - - 5555h aah - - 4 write - - 2a aah 55h - - 5 write - - 5555h 60h - - pause 10 m s pause 10 m s pause 10 m s software product identification and boot block lockout detection acquisition flow product identification entry (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 60 to address 5555 product identification and boot block lockout detection mode (3) read address = 00000 data = da read address = 00001 data = 45 read address = 00002 data = ff/fe (4) read address = 3fff2 data = ff/fe (5) product identification exit (1) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 pause 10 s normal mode (6) (2) (2) pause 10 s m m notes for software product identification/boot block lockout detection: (1) data format: dq7 - dq0 (hex); address format: a14 - a0 (hex) (2) a1 - a16 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block (address 0002 hex/3fff2 hex res pond to first 8k/last 8k) lockout detection mode if power down. (4), (5) if the output data is "ff hex," the boot block programming lockout feature is activated; if the output data "fe hex," the lockout feature is inactivated and the block can be programmed. (6) the device returns to standard operation mode. (7) this product supports both the jedec standard 3 byte command code sequence and original 6 byte command code sequence. for new designs, winbond recommends that the 3 byte command code seque nce be used.
w29c020c publication release date: april 2000 - 9 - revision a2 command codes for boot block lockout enable byte sequence boot block lockout f eature set on first 8k address boo t block boot block lockout f eature set on last 8k address b oot block address data address data 0 write 5555h aah 5555h aah 1 write 2aaah 55h 2aaah 55h 2 write 5555h 80h 5555h 80h 3 write 5555h aah 5555h aah 4 write 2aaah 55h 2aaah 55h 5 write 5555h 40h 5555h 40h 6 write 00000h 00h 3ffffh ffh pause 10 m s pause 10 m s boot block lockout enable acquisition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 10 ms load data 00 to address 00000 boot block lockout feature set on first 8k address boot block boot block lockout feature set on last 8k address boot block load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 10 ms load data ff to address 3ffff notes for boot block lockout enable: 1. data format: dq7 - dq0 (hex) 2. address format: a14 - a0 (hex) 3. if you have any questions about this commend sequence, please contact the local distributor or winbond electronics corp.
w29c020c - 10 - dc characteristics absolute maximum ratings parameter rating unit power supply voltage to v ss potential - 0.5 to +7.0 v operating temperature 0 to +70 c storage temperature - 65 to +150 c d.c. voltage on any pin to ground potential except a9 - 0.5 to v dd +1.0 v transient voltage (<20 ns ) on any pin to ground potential - 1.0 to v dd +1.0 v voltage on a9 and oe pin to ground potential - 0.5 to 12.5 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. operating characteristics (v dd = 5.0v 10 % , v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions limits unit min. typ. max. power supply current i cc ce = oe = v il , we = v ih , all dqs open address inputs = v il /v ih , at f = 5 mhz - - 50 ma s tandby v dd current (ttl input) i sb 1 ce = v ih , all dqs open other inputs = v il /v ih - 2 3 ma standby v dd current (cmos input) i sb 2 ce = v dd - 0.3v, all dqs open - 20 100 m a input leakage current i li v in = gnd to v dd - - 10 m a output leakage current i lo v in = gnd to v dd - - 10 m a input low voltage v il - - - 0.8 v input high voltage v ih - 2.0 - - v output low voltage v ol i ol = 2.0 ma - - 0.45 v output high voltage v oh1 i oh = - 400 m a 2.4 - - v output high voltage cmos v oh2 i oh = - 100 m a; v cc = 4.5v 4.2 - - v
w29c020c publication release date: april 2000 - 11 - revision a2 power - up timing parameter symbol typical unit power - up to read operation t pu . read 100 m s power - up to write operation t pu . write 5 ms capacitance (v dd = 5.0v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit dq pin capacitance c dq v dq = 0v 12 pf input pin capacitance c in v in = 0v 6 pf ac characteristics ac test conditions (v dd = 5.0v 10 % for 90 ns and 120 ns; v dd = 5.0v 5% for 70 ns) parameter conditions input pulse levels 0v to 3v input rise/fall time <5 ns input/output ti ming level 1.5v/1.5v output load 1 ttl gate and c l = 100 pf for 90/120 ns c l = 30 pf for 70 ns ac test load and waveform +5v 1.8k 1.3k d out w w 100 pf for 90/120 ns 30 pf for 70 ns (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output
w29c020c - 12 - ac characteristics, continued read cycle timing parameters (v dd = 5.0v 10 % for 90 ns and 120 ns; v dd = 5.0v 5% for 70 ns, v ss = 0v, t a = 0 to 70 c) parameter sym. w29c020c - 70 w29c020c - 90 w29c020c - 12 unit min. max. min. max. min. max. read cycle time t rc 70 - 90 - 120 - ns chip enable access time t ce - 70 - 90 - 120 ns address access time t aa - 70 - 90 - 12 0 ns output enable access time t oe - 35 - 40 - 50 ns ce high to high - z output t chz - 25 - 25 - 30 ns oe high to high - z output t ohz - 25 - 25 - 30 ns output hold from address change t oh 0 - 0 - 0 - ns byte/page - write cycle timing parameters parameter symbol min. typ. max. unit write cycle (erase and program) t wc - - 10 ms address setup time t as 0 - - ns address hold time t ah 50 - - ns we and ce setup time t cs 0 - - ns we and ce hold time t ch 0 - - ns oe high setup time t oes 0 - - ns oe high hold time t oeh 0 - - ns ce pulse width t cp 70 - - ns we pulse width t wp 70 - - ns we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 0 - - ns byte load cycle time t blc - - 200 m s note: all ac timing signals observe the following guideline for determining setup and hold times: r eference level is v ih for high - level signal and v il for low - level signal.
w29c020c publication release date: april 2000 - 13 - revision a2 ac characteristics, continued data polling characteristics (1) parameter symbol min. typ. max. unit data hold time t dh 10 - - ns oe hold time t oeh 10 - - ns oe to output delay (2) t oe - - - ns write recovery time t wr 0 - - ns notes: (1) these parameters are characterized and not 100% tested. (2) see t oe spec in a.c. read cycle timing parameters . toggle bit characteristics (1) parameter symbol min. typ. max. unit data hold time t dh 10 - - ns oe hold time t oeh 10 - - ns oe to output delay (2) t oe - - - ns oe high pulse t oehp 150 - - ns write recovery time t wr 0 - - ns notes: (1) these parameters are characterized and not 100% tested. (2) see t oe spec in a.c. read cycle timing parameters . timing waveforms read cycle timing diagram address a17-0 dq7-0 data valid data valid high-z ce oe we t rc v ih t oe t ce t oh t aa t chz t ohz high-z
w29c020c - 14 - timing waveforms, continued we control led write cycle timing diagram address a17-0 dq7-0 data valid internal write starts ce oe we t as t cs t oes t ah t wc t ch t oeh t wph t wp t ds t dh ce controlled write cycle timing diagram high z data valid internal write starts address a17-0 ce oe we t as t ah t wc t oeh t dh t ds t cp t oes dq7-0 t wph t cs t ch
w29c020c publication release date: april 2000 - 15 - revision a2 timing waveforms, continued page write cycle timing diagram address a17-0 byte 0 byte 1 byte 2 byte n-1 byte n internal write start dq7-0 ce oe we t wc t blc t wph t wp data polling timing diagram address a15-0 dq7 we oe ce t dh t oeh t oe high-z t wr
w29c020c - 16 - timing waveforms, continued toggle bit timing diagram dq6 we oe ce t dh t oe high-z t wr t oeh page write timing diagram software data protection mode 5555 5555 aa 55 a0 three-byte sequence for software data protection mode byte/page load cycle starts internal write starts word n (last word) word 0 sw2 sw1 sw0 address a15-0 dq7-0 ce oe we 2aaa t wp t wph t blc word n-1 t wc
w29c020c publication release date: april 2000 - 17 - revision a2 t iming waveforms, continued reset software data protection timing diagram sw2 sw1 sw0 address a15-0 dq7-0 ce oe we sw3 sw4 sw5 internal programming starts six-byte sequence for resetting software data protection mode t wc t wp t wph t blc 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 20 software chip erase timing diagram sw2 sw1 sw0 address a15-0 dq7-0 ce oe we sw3 sw4 sw5 internal erasing starts six-byte code for 5v-only software chip erase t wc t wp t wph t blc 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10
w29c020c - 18 - ordering information part no. access time ( n s) power supply current max. ( m a) standby v dd current max. ( m a) package cycling w29c020c - 70b 70 50 100 600 mil dip 10k w29c020c - 90b 90 50 100 600 mil dip 10k w29c020c - 12b 120 50 100 600 mil dip 10k w29c020ct70b 70 50 100 type one tsop 10k w29c020ct90b 90 50 100 type one tsop 10k w29c020ct12b 120 50 100 type one tsop 10k w29c020cp70b 70 50 100 32 - pin plcc 10k w29c020cp90b 90 50 100 32 - pin plcc 10k w29c020cp12b 120 50 100 32 - pin plcc 10k notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w29c020c publication release date: april 2000 - 19 - revision a2 package dimensions 32 - pin p - dip 1.dimensions d max. & s include mold flash or tie bar burrs. 2.dimension e1 does not include interlead flash. 3.dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6.general appearance spec. should be based on final visual inspection spec. . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4.dimension b1 does not include dambar 5.controlling dimension: inches. 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 32 - pin tsop a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) q min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm q __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
w29c020c - 20 - package dimensions, continued 32 - pin plcc l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 notes: 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches. 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
w29c020c publication release date: april 2000 - 21 - revision a2 version history version date page description a1 may 1999 - initial issued a2 apr. 2000 12 change byte load cycle time from 150 m s to 200 m s headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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